Method of manufacturing a nonvolatile semiconductor memory device and select gate device having a stacked gate structure

ABSTRACT

A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isolate stripe-shaped element-forming regions. Formed on the substrate area floating gate via a first gate insulating film and further a control gate via a second gate insulating film. Source and drain diffusion layers are formed in self-alignment with control gates. The second gate insulating film on the floating gate is divided and separated together with the floating gate by slits above the element isolation/insulation films into discrete portions of individual memory cells. The select gate is formed with a STI recess process in advance locally in the select area.

CROSS REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. Pat. No. 6,720,610, and U.S. Pat. No. 5,150,178.

FIELD OF THE INVENTION

The present invention generally relates to nonvolatile semiconductor memory device. More particularly, it pertains to a method and structure for an improve NAND select gate formation.

BACKGROUND OF THE INVENTION

This invention relates to a nonvolatile semiconductor memory device and its manufacturing method.

There is known an electrically rewritable, nonvolatile semiconductor memory (Flash) using memory cells of a stacked-gate structure stacking floating gates and control gates. This kind of Flash uses a tunneling insulation film as a first gate insulating film between floating gates and a semiconductor substrate and typically uses, as the second gate insulating film between floating gates and control gates, an ONO film which is a multi-layered film of a silicon oxide film (O) on a silicon nitride film (N) on a silicon oxide film (O).

Each memory cell is formed in an element-forming region partitioned by an element isolation/insulation film. In general, a floating gate electrode film is divided in the direction of control gate line (word line) by making a slit on the element isolation/insulation film. In the step of making the slit, division of floating gates in the bite-line direction is not yet done. Then a control gate electrode film is stacked via an ONO film on all surfaces of the substrate including the top of the slit-processed floating gate electrode film, and by sequentially etching the control gate electrode film, ONO film, and floating gate electrode film, control gates and floating gates are then isolated in the bit-line direction. After that, source and drain diffusion layers are formed in self-align-ment with the control gates.

SUMMARY OF THE INVENTION

It is therefore an object of the invention to provide a nonvolatile semiconductor memory device improved in reliability by preventing destruction of data caused by movements of electric charges between floating gates, and also relates to its manufacturing method.

According to the first aspect of the invention, there is provided a nonvolatile semiconductor memory device comprising:

a semiconductor substrate;

a plurality of element-forming regions partitioned by element isolation/insulation films in said semiconductor substrate;

floating gates formed in said element-forming regions via a first gate insulating film and separated for individual said element-forming regions;

second gate insulating films formed on said floating gates, and divided and separated above said element isolation/insulation films;

control gates formed on said floating gates via said second gate insulating films; and source and drain diffusion layers formed in self-alignment with said control gates.

According to the second aspect of the invention, there is provided a nonvolatile semiconductor memory device comprising:

a semiconductor substrate; a plurality of element-forming regions partitioned by element isolation/insulation films in said semiconductor substrate;

floating gates formed in said element-forming regions via a first gate insulating film and separated for individual said element-forming regions;

second gate insulating films formed on said floating gates to continuously extend over a plurality of element-forming regions along recesses made into surfaces of said element isolation/insulation films;

control gates formed on said floating gates via said second gate insulating films; and source and drain diffusion layers formed in self-alignment with said control gates.

According to the third aspect of the invention, there is provided a manufacturing method of a nonvolatile semiconductor memory device, comprising the steps of:

making element isolation/insulation films that partition element-forming regions in a semiconductor substrate;

stacking a first gate electrode material film and a second gate insulating film on said semiconductor substrate via a first gate insulating film;

etching said second gate insulating film and the underlying first gate electrode material film to make slits that separate said first gate electrode material film above said element isolation/insulation films;

forming an insulating film on side surfaces of said first gate electrode material film, and thereafter stacking a second gate electrode material film;

sequentially etching said second gate electrode material film, said second gate insulating film and first gate electrode material film to pattern said first gate electrode film into floating gates and said second gate electrode material film into control gates;

and making source and drain diffusion layers in self alignment with said control gates.

According to the fourth aspect of the invention, there is provided a manufacturing method of a nonvolatile semiconductor memory device, comprising the steps of: making element isolation/insulation films that partition element-forming regions in a semiconductor substrate;

stacking a first gate electrode material film on said semiconductor substrate via a first gate insulating film;

etching said first gate electrode material film to make slits that separate said first gate electrode material film on said element isolation/insulation films;

etching surfaces of said element isolation/insulation films exposed to said slits to make recesses;

stacking a second gate electrode material film on said first gate electrode material film and said element isolation/insulation films via said first gate insulating film;

sequentially etching said second gate electrode material film, said gate insulating film and said first gate electrode material film to pattern said first gate electrode material film into floating gates and said second gate electrode material film into control gates;

and making source and drain diffusion layers in self-alignment with said control gates.

According to the fifth aspect of the invention, there is provided a manufacturing method of a select gate. Semiconductor device, comprising the steps of: making element isolation/insulation films that partitions element-forming regions in a semiconductor substate; stacking a first gate electrode material film on said semiconductor Substrate via a first gate insulating film; second gate insulating films formed on said, First gate electrode film, and second gate formed on said, First gate via said second gate insulating film, and source and drain diffusion area formed in self-alignment with said select gate.

According to the invention, by partially etching element insulation films in the select gate area, followed by first gate formed in said element-forming region and select gate region via a first gate insulating film, and followed by a CMP (Chemical Mechanical Polish) process, both non-volatile memory floating gate and select gate device is hereby formed simultaneously.

second gate insulating films formed on said floating gates and control gate devices;

control gates formed on said floating gates via said second gate insulating films; and

source and drain diffusion layers formed in self-alignment with said control gates.

Thereby, also when memory cells are miniaturized, the invention allows the process to be simple and reduce the defect density.

BRIEF DESCRIPTION OF THE DRAWINGS

The above objects and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments, and by reference to the attached drawings in which:

FIG. 1 is a plan view of the layout of a NAND nonvolatile memory device;

FIGS. 2A and 2B are sectional views, respectively taken along lines III-III′ and IV-IV′ of FIG. 1, of a nonvolatile memory device and select device;

FIGS. 3A through 5B are sectional views, taken along lines III-III′ (for FIGS. 3A, 4A, and 5A) and IV-IV′ (for FIGS. 3B, 4B, and 5B), for illustrating a method of manufacturing a nonvolatile memory device;

FIG. 6 is a plan view of the layout of a nonvolatile memory device according to the present invention;

FIG. 7 is sectional view, taken along line VI-VI′ of FIG. 6, of a select device according to the present invention;

FIGS. 8A through 10B are sectional views, taken along lines VI-VI′ (for FIGS. 8A, 9A, and 10A) and VII-VII′ (for FIGS. 8B, 9B, and 10B), for illustrating a method of manufacturing a nonvolatile memory device according to the present invention;

DETAILED DESCRIPTION OF THE INVENTION

Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention.

The embodiments are described below by reference to NAND type nonvolatile memory devices.

FIGS. 2A and 2B are sectional views, respectively taken along lines III-III′ and IV-IV′ of FIG. 1, of a nonvolatile memory device and select device. FIG. 2A is a sectional view taken along line III-III′ of FIG. 1, and FIG. 2B is a sectional view taken along line IV-IV′. In FIGS. 2A and 2B, reference numeral 101 denotes a P-type semiconductor substrate, reference numeral 107 denotes an N-well, reference numeral 201 denotes a P-well, reference numeral 301 denotes a field oxide film for dividing the semiconductor substrate into an active region and a non-active region, reference numeral 350 denotes a gate insulating film, reference numeral 370 denotes a source/drain region, reference numeral 401 denotes a floating gate, reference numeral 450 denotes an interdielectric layer, reference numeral 501 denotes a control gate, reference numeral 600 denotes a first insulating film.

Referring to the respective sectional views in FIGS. 2A and 2B, on the P-type (or alternatively, N-type) semiconductor substrate 101, ion implantation is performed at various steps, and the field oxide 301, gate insulation 350, floating gate 401, interdielectric layer 450, and control gate 501 are sequentially deposited. On each side of the gates, N-type (or alternatively, P-type) source/drain regions 370 are formed. The first insulating film 600 are formed on the source/drain regions 370, on the sidewalls of both the floating gate 401 and control gate 501, and on top of the control gate 501. The first insulating film 600 acts as a dielectric layer for electrically isolating the source/drain 370, the floating gate 401, and the control gate 501 from the PA-plate 700. The first insulating film 600 has a predetermined permittivity and may consist of, for example, an oxide film, a nitride film, an oxynitride film, an oxide-nitride-oxide laminate (ONO) films or a combination of such films such as a nitride film and an oxide film. Of course, other suitable insulating materials may be used.

FIGS. 3A through 5B are sectional views for illustrating the manufacturing method of a nonvolatile memory device according to a first embodiment of the present invention. Here, FIGS. 3A, 4A and 5A are sectional views taken along line III-III′ of FIG. 1, and FIGS. 3B, 4B and 5B are sectional views taken along line IV-IV′ of FIG. 1.

FIGS. 3A and 3B show the step of forming a field oxide film 301 and a gate oxide film 350 on a P-type portion 201 of a semiconductor substrate 101. Alternatively, the structures may be formed on an N-type portion of a semiconductor substrate without departing from the scope of this invention.

Referring to FIGS. 3A and 3B, a second conductivity type well 107 is formed in a first conductivity type semiconductor substrate 101, and a first conductivity type well 201 is formed in the second conductivity type well 107. A field oxide film 301 is formed on a surface of the substrate where the first and second conductivity type wells are formed, for electrically isolating the active devices, and a gate oxide film 350 is formed on the resultant structure. Of course, it may be possible to form the gate oxide film 350 before forming the field oxide film 301, but this is generally not as practical.

For example, in FIGS. 3A and 3B, N-type impurities are implanted into a predetermined region of a P-type semiconductor substrate 101 using photolithography and ion-implantation. Then, the ion-implanted region is diffused to a desired depth by heat treating at a high temperature, to thereby form the N-well 107. Then, the P-well 201 is formed using the same method on a predetermined region of the N-well 107. Next, the isolation film 301 is formed by a typical isolation method, for example, shallow trench isolation (STI), and a thin thermal oxide film is grown on the entire surface of the formed isolation film, to thereby form a gate oxide film 350.

FIGS. 4A and 4B show the steps of forming a floating gate 401, an interdielectric layer 450, and a control gate 501 according to the first embodiment. A floating gate 401 is formed on the gate oxide film 350; an interdielectric layer 450 having a predetermined thickness is formed on isolation film 301, gate oxide film 350, and floating gate 401; and control gate 501 is formed on the interdielectric layer 450.

For example, in FIGS. 4A and 4B, conductive material for forming a gate electrode, such as polysilicon doped with impurities, is deposited on the gate oxide film 350, and the polysilicon is patterned by chemical mechanical polish (CMP) for forming a floating gate, to thereby form the floating gate 401. An insulation film is deposited on the floating gate 401, such as a sequentially deposited oxide film, nitride film and oxide film (ONO film), to thereby form an interdielectric layer 450. The interdielectric layer 450 insulates the floating gate 401 from the control gate 501, and acts as a dielectric layer over the floating gate 401.

The select transistors operate as typical transistors rather than as floating gate storage devices. Therefore, in the areas where select transistors are to be formed part of, the control gate 501 and interdielectric 450 is patterned to create contact holes so that contact can be connected to 401 for the select transistor.

FIG. 6 represents the plan view of the primary embodiment of this invention.

FIG. 7A is a sectional view taken along line VI-VI′ of FIG. 6, where the select transistor is fabricated for the operation as typical transistors. The conductor 401 must be continuous across transistors. In order to distinguish the select gate area, an additional mask RCS in FIG. 6 is applied for field oxide recess after isolation formation.

FIGS. 8A through 10B are sectional views for illustrating the manufacturing method of a select gate area according to this invention. Here FIGS. 8A, 9A, 10A are sectional views taken along line VI-VI′ of FIG. 6, and FIGS. 8B, 9B, 10B are sectional views taken along ling VII-VII′ of FIG. 6.

FIGS. 8A and 8B show the step of recessing a field oxide film 301 in the select gate area, while maintaining the filed oxide film 301 in the floating fate area. In the select gate area in FIG. 8A, the field oxide is recessed by and additional oxide etch, while the floating gate area is covered by photo resist during the oxide recess etch. This step is inserted after STI (field trench isolation) CMP process, and before STI pad nitride 800 removal. Alternatively, the structures may be formed on an N-type portion of a semiconductor substrate without departing form the scope of this invention.

FIGS. 9A and 9B show the step of depositing a floating gate material 401 in the select gate and floating gate area. Due to the recess of field oxide film 301 in the select gate area, the floating gate 401 in the select gate area is relatively flat, compared to the bumpy floating gate material 401 in the floating gate area, which is taller on the top of field oxide.

In FIGS. 10A and 10B, a chemical mechanical polish process is applied are both select gate area and floating gate area. In FIG. 10A, the poly silicon remains continuous in order to function as a traditional transistor due to the recess of field oxide process. In FIG. 10B, the poly silicon is divided into isolated floating gate by the tall field oxide (or STI) in the floating gate area. An insulation film is thereby deposited on the floating gate 401 such as a sequentially deposited oxide film, nitride film and oxide film (ONO film), to thereby form an interdielectric layer 450. The interdierectric layer 450 insulates the floating gate and select gate from the control gate 501, and acts as a dielectric layer over the floating gate to control. The subsequent process will be thereafter identical to the prior art as mentioned in FIGS. 1 to 5, but not limited to. 

1. A non-volatile semiconductor device structure comprising: a semiconductor substrate; a plurality of element-forming regions partitioned by element isolation/insulation films in said semiconductor substrate; floating gates formed in said element-forming regions via a first gate insulating film and separated for individual said element-forming regions; Second gate insulating films formed on said floating gates, and divided and separated above said element isolation/insulation films; Control gates formed on said floating gates via said second gate insulating films; and source and drain diffusion layers formed in self-alignment with said control gates.
 2. The method according to claim 1, wherein the floating gate is divided and separated by increasing the height of element insulation films (301), followed by first gate formed in said element-forming region via a first gate insulating film, and followed by a CMP (Chemical Mechanical Polish) process to divide and separate the floating gates.
 3. The method according to claim 2, wherein the division and separation of floating gates is processed by floating gate material etch back process.
 4. The method according to claim 2, wherein the height of element insulation films (301) is increased for the division and separation of floating gates during CMP or floating gate material etch back process.
 5. The method according to claim 2, wherein the height of element insulation films (301) is increased by increasing the thickness of STI pad nitride 800, or reducing the oxide loss after STI pad nitride removal
 6. A semiconductor device structure for select gate comprising: forming a first layer of polysilicon over a tunnel oxide layer, said tunnel oxide layer being situated on a substrate; the first layer of polysilicon is not patterned during the division and separation of floating gates; fabricating an ONO stack and 2nd layer of polysilicon over said first layer of polysilicon; the 2nd layer of polysilicon can either be electrically connected to 1st layer of polisilicon or not.
 7. The method according to claim 6 wherein said the 1st polysilicon in select gate area is protected during the process of division and separation of floating gates.
 8. The method according to claim 7, wherein the height of element insulation films (301) in the select gate area is intentionally reduced before the formation of a first gate insulating film.
 9. The method according to claim 8, wherein the reduction of the height of element insulation films (301) can be either by wet etch process or dry etch process
 10. The method according to claim 2 and claim 7, wherein the height of element insulation films in non-volatile semiconductor device area is protected during the reduction of the height of element insulation films (301) in the select gate area.
 11. The method according to claim 10, wherein the height of element insulation films in non-volatile semiconductor device area can be protected by photoresist, while the select gate area is exposed to the etch process 